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HFBR-707X2DEM
10 Gb Ethernet, 1310 nm, 10GBASE-LRM, X2 Transceiver
Data Sheet
Description
The X2 LRM fiber optic transceiver is an "intelligent" optical module which incorporates the complete physical layer functionality of 10GbE on multi mode fiber with data rate of 10.3Gbps. The X2 LRM module includes a transmitter that incorporates an uncooled, directly modulated 1.3 m Fabry-Perot laser. The receiver subassembly includes a PIN photodiode and a linear/AGC trans-impedance amplifier. To cope with the effect of modal dispersion of multi mode fibers at 10 Gbps over the distances specified in the IEEE 802.3aq LRM standard, an electronic dispersion compensation circuit is used. The MUX/DEMUX, XAUI interface and MDIO management functions are all integrated into the module, as is a precision oscillator. The module is compliant to the X2 Multi Source Agreement specifications.
Features
* Compliant with IEEE LRM Standard - Draft P802.3aqTM/D4.0 for Type 10GBASE-LRM * Compliant with X2 MSA Issue 2.0b * Standard SC Duplex fiber optic connector * Standard 70 pin electrical connector * Four wide XAUI Electrical interface * MDIO Management Interface * Front Panel hot pluggable * Digital Optical Monitoring (DOM) provides Tx/Rx power, laser bias current, and module temperature
Specifications
* 220m reach on OM1, 0M2 and OM3 Multimode Fiber Cables * Total Power Dissipation less than 4W
Applications
* Ethernet switching systems * Ethernet peripheral interface * Computer system I/O
General Specifications
Optics PIN TIA
EDC 802.3ae SerDes LD Micro I2C MDIO Other Signals
Rx
ROSA Optics Laser TOSA
Tx System Control
Figure 1. High level block diagram
General Optical Specifications
Optical Connector: SC Duplex Optical Line rate: 10.3125 Gb/s Link Length: 220m, with 62.5um MMF/ 160/500MHz*km 220m, with 50um MMF/ 500/500MHz*km 220m, with 50um MMF/ 1500/500MHz*km Laser: 1310nm FP Laser Detector: PIN diode
General Electrical Specifications
Connector: 70-pin, mates to Tyco/AMP Part No. 1367337-1 or equivalent Supply Voltages: +5 V, +3.3 V and APS E->O Coding (Transmit Direction): 8B/10B coding removed, 64B/66B added O->E Coding (Receive Direction): 64B/66B removed, 8B/10B coding added XAUI interface: 100 W Differential, AC- coupled I/O on Tx and Rx, per IEEE 802.3ae Clause 47 Control interface: MDIO, 1.2 V, per IEEE 802.3ae Clause 45.3 Non Volatile memory: 48 byte user space
Environmental Specifications
Operating temperature: 0 C to +70 C case Power consumption: 4.0 W maximum
2
Technical Specifications Absolute Maximum Ratings1
Parameter
Storage Temperature Operating Temperature Supply Voltage (5 V) Supply Voltage (3.3 V) Supply Voltage (APS) Voltage on any XAUI pin Voltage on any LVCMOS pin Received Average Power -0.7
Minimum
-40 0
Typical
Maximum
85 70 5.5 3.6 2.0 2.5 4.0 1.5
Units
C C V V V V V dBm
Notes
Case temperature
Recommended Operating Conditions2
Parameter
Initialization Time Supply Voltage (5 V) Supply Voltage (3.3 V) Supply Voltage (APS) Supply Current (5 V) Supply Current (3.3 V) Supply Current (APS) Power Consumption Supply Current Ramp Rate Inrush current (per power supply) 1 0.74 0.66 3.0 0.9 0.8 4 50 150% steady state rating 4.75 3.14
Minimum
Typical
0.5 5 3.3
Maximum
5 5.25 3.47
Units
sec V V V mA A A W mA/ms A
Notes
3
4
Notes: 1. Absolute maximum ratings are those values beyond which functional performance is not intended, device reliability is not implied, and damage to the device may occur. 2. Typical operating conditions are those values for which functional performance and device reliability is implied. 3. X2 MSA compliant. 4. Not applicable to inrush current due to small transceiver capacitive load presented to the host during hot plug which limits the total in rush charge.
3
Transmitter Path Summary
Figure 2 shows a block diagram of the transmit path, from the four XAUI differential inputs to the optical output. The incoming XAUI differential 8B/10B encoded electrical inputs, are reformatted and transmitted onto the outgoing fiber optic interface using 64B/66B encoding.
Receiver Path Summary
Figure 3 shows a block diagram of the receiver path, from the incoming 10.3 Gb/s, 64B/66B encoded optical interface to the four 3.125 Gb/s differential 8B/10B encoded XAUI electrical output interface. The XAUI output drivers provide low-swing differential output with 100 W differential output impedance and are ac coupled.
Tx XTAL PLL
SIPO and code word alignment, with |K| char
XAUI LANE 0
CDR
Lane Alignment, with |A| character.
Rate adjust by add drop off |R| character
64B/66B 1:0 Block sync
8B/10B Decoder
39+X 58
Scrambler 1+X
Rate Adjust & Frame
64B/66B Encoder
PLL
Tx Opto
XAUI LANE 1
XAUI LANE 2
XAUI LANE 3
Figure 2. Transmit Path High Level Overview
Driver
Rate adjust
XAUI LANE 0
8B/10B Encoder
Mux
Frame Recovery (block sync)
64B/66B Decoder
Descrambler 1+X
39 +X 58
De Mux
Mux
XTAL
PLL
XAUI LANE 1
EDC
Rx Opto
XAUI LANE 2
Clock for Rx 10G path
XAUI LANE 3
Figure 3. Receive Path High Level Overview
4
CDR
Optical Specifications
Parameter
Transmitter Signaling Speed - nominal Signaling Speed variation from nominal Center Wavelength RMS Spectral Width at 1260 nm RMS Spectral Width between 1260 nm and 1300 nm RMS Spectral Width between 1300 nm and 1355 nm Launch Power (OMA) Average Launch Power Average Launch Power of OFF transmitter Extinction Ratio Peak Launch Power RIN20OMA Eye Mask parameters {X1, X2, X3, Y1, Y2, Y3} Transmitter Waveform and Dispersion Penalty (TWDP) Uncorrelated Jitter (rms) Encircled Flux within 5m radius Encircled Flux within 11m radius Optical Return Loss Tolerance Receiver Signaling Speed - nominal Signaling Speed variation from nominal Center Wavelength Stressed Sensitivity (OMA) Stressed Sensitivity (OMA) for symmetrical test Overload (OMA) Receiver Reflectance Signal Detect On (OMA)
1.5 -12 -7 -100 1260 10.3125 +100 1355 -6.5 -6 30 81 20 3.5 3 -128 {0.25, 0.40, 0.45, 0.25, 0.28, 0.80} 4.7 0.033 -4.5 -6.5 4 1.5 0.5 -30 -100 1260 10.3125 +100 1355 2.4
Minimum
Typical
Maximum
Units
GBd ppm nm nm
Notes
1 1, See Figure 4a
nm dBm dBm dBm dB dBm dB/Hz
1 2, See Figure 4b 2, See Figure 4b
2, 3 See Figure 4c
dB UI % % dB GBd ppm nm dBm dBm dBm dB dBm 7 5 6 4 4
Notes: 1. RMS spectral width is the standard deviations of the spectrum. 2. The OMA, average launch power and peak launch power specifications apply at TP2. This is after each type of patch cord. For information: Patch cord losses, between MDI and TP2, differ. The range of losses must be accounted for to ensure compliance to TP2. 3. Peak optical power can be determined as the maximum value from the waveform capture from the TWDP test, or equivalent method. 4. This encircled flux specification, measured per IEC 61280-1-4, defines the near field light distribution at TP2 when the MDI is coupled directly into the appropriate patch cord. 5. This value will be met for several different independent test conditions defined in Section 68 of the IEEE 802.3aqTM/D4.0: 1. Comprehensive stressed receiver test (two separate conditions; Pre-Cursor and Post-Cursor tap weights); 2. Simple stressed receiver test; 3. Jitter tolerance (two separate frequency/p-p amplitude conditions) 6. This value will be met for test conditions defined in Section 68 of the IEEE 802.3aqTM/D4.0 for comprehensive stressed receiver test symmetrical tap weights. 7. With ER 10dB.
5
4
1+Y3
RMS spectral width (nm)
3
2 1 Normalized Amplitude 1 1-Y1 1-Y2 0.5 Y2 Y1 0
Maximum allowed rms spectral width
0 1260 1280 1300 1320 Wavelength (nm) 1340 1360
Figure 4a. 10GBASE-LRM Transmitter spectral limits
-Y3 0 X1 X2 X3 1-X3 1-X2 1-X1 1
Normalized Time (Unit Interval) Note: where X1, X2, X3, Y1, Y2, Y3 = 0.25, 0.40, 0.45, 0.25, 0.28, 0.80 respectively Figure 4c. Transmitter Eye Mask Definition 1 Maximum: 0.5 dBm 0 -1 Average launch power (dBm) -2 -3 -4 -5 -6 Minimum: -6.5 dBm -7 -8 Extinction ratio infinite Extinction ration of 10 dB (example) Extinction ratio, minimum (3.5 dB)
-5 Minimum: -4.5 dBm
-4
-3
-2
-1
0
1 Maximum 1.5 dBm
2
Launch power in OMA (dBm)
Figure 4b. Graphical representation of approximate region of transmitter compliance
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Electrical Control and Sense I/O Parameters Table 1. CMOS DC Parameters (MDC, PRTAD<4:0>, LASI)
Parameter
Vol Voh Vih Vil Ipd Trise Tfall
Description
Output low voltage Output high voltage Input high voltage Input low voltage Input pad pulldown current Rise time Fall time
Minimum
1.0 0.84
Typical
Maximum
0.15 1.5 1.25 0.36
Units
V V V V A ns ns
Conditions
ext. Rpullup = 10 kW to 1.2 V ext. Rpullup = 10 kW to 1.2V
20
40
120 30
Vin = 1.2 V Cload = 300 pF Cload = 300 pF
25
50
Electrical MDIO Parameters Table 2. MDIO 1.2 V dc parameters
Parameter
Voh Vol Iol Vih Vil Cin
Description
Output high voltage Output low voltage Output low current Input high voltage Input low voltage Input capacitance
Minimum
1.0 -0.3 -4 0.84 -0.3
Typical
Maximum
1.5 0.2
Units
V V mA
Conditions
Ioh = -100 uA Iol = +100 uA Vin = 0.3
1.5 0.36 10
V V pF
Table 3. MDIO AC Parameters
Parameter
Thold Tsetup Tdelay Fmax
Description
MDIO data hold time MDIO data setup time Delay from MDC rising edge to MDIO data change Maximum MDC clock rate
Minimum
10 10 0
Typical
Maximum
Units
ns ns
Conditions
300 2.5
ns MHz
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Electrical High Speed I/O Parameters Table 4. XAUI Input Interface
Parameter Description
BAUD rate for 10Gb E BAUD rate tolerance Differential input amplitude Differential return loss Common mode return loss Input Differential Skew Jitter amplitude tolerancedeterministic + random jitter +Sj jitter -100 200
Minimum
Typical
3.125
Maximum
100 2500 -10 -6 75 0.55 + Sj
Units
Gb/s ppm mVpp dB dB ps P-P UIpp
Conditions
Note 1 100 MHz to 2.5 GHz ref to 100W impedance 100 MHz to 2.5 GHz ref to 25W at crossing point, Note 2 See Figure 5a for SJ jitter graph
Table 5. XAUI Driver Characteristics
Parameter Description
BAUD rate for 10Gb E BAUD rate variation Differential amplitude Transition times (20-80%) Total output jitter Output deterministic jitter Output differential skew Differential output return loss -100 800 60 90
Minimum
Typical
3.125
Maximum
100 1600 130 0.175 0.085 15
Units
Gb/s ppm mVpp ps UI UI ps dB
Conditions
Note 2 no pre-equalization no pre-equalization at crossing point 312.5 MHz to 625 MHz: -10 dB625 MHz to 3.125 GHz: as per equation 47-1 IEEE 802.3ae See Figure 5b
Electrical eye mask
Note: 1. Maximum amplitude of 2500 mVpp is the combined effect of the driver maximum output signal of 1600 mVpp and the receiver input impedance mismatch. 2. For information only.
Figure 5a. Single-tone sinusoidal jitter mask
8
Electrical Eye Mask
800
DIFFERENTIAL AMPLITUDE (mV)
400
0
-400
-800 0 X1 = 0.175 X2 = 0.390 1-X2 = 0.610 TIME IN UI 1-X1 = 0.825 1
Figure 5b. XAUI Driver Near End Template
General Connector Considerations
1. Ground connections are common for Tx and Rx. 2. VCC contacts are each rated at 0.5 A nominal. 3. See Figure 6 for location of Pin 1.
Table 6. DOM Accuracy
Parameter
Rx Power Range Output Power Range Temperature Range Ibias Range
Accuracy Specification (typ)
1.5 dBm 2 dBm 3 C (-5 C to +75 C) 5% (2 mA to 80 mA)
Accuracy Specification (max)
2 dBm 3 dBm 5 C 10%
9
EEPROM and NVR Content
X2 Module contains Non-Volatile (NVR) and Volatile memory in accordance with the Xenpak MSA rev 3.0, the IEEE 802.3ae Standard and applicable end-user specifications.
Table 7. Customer specific NVR Content - Device 1 PMA/PMD Registers: 0x8012 - 0x805C
Data Address (Hex)
0x8012 0x8013 0x8014 0x8015 0x8017 0x8018 0x8022 0x8024 0x8026 0x803A 0x804A 0x805C
Field Size (Bytes)
1 1 1 2 1 1 2 1 3 16 16 16
Name of Field
Tcvr Type Connector Encoding Bit Rate Protocol Compliance Range Fiber Type Wavelength Vendor Name Vendor PN Vendor SN
Value (Hex)
02 01 01 28 48 01 00 00 16 01 01 FF B8 41 56 41 47 4F 20 20 2020 20 20 20 20 20 20 20 48 46 42 52 2D 37 30 3758 32 44 45 4D 20 20 20 AGAyywwXnnn 20 20 20 20 20
Remark
Transceiver Type (X2=02) Optical Connector Type (SC=01) Bit Encoding (NRZ=01) Bit rate: in multiples of 1 MB/s Protocol Type (10GbE=01) "Unspecified" : 10GbE code 0 "220m for MMF" "MM, generic" Center Wavelength : 1310nm AVAGO HFBR-707X2DEM yy: year; ww: work week; nnn:rolling serial number from 000 to ZZZ
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Table 8. General I/O Pin Summary
Signal Type
Power Supply Pins Ground 3.3 V 5.0 V Adaptive power supply Adaptive power supply set Adaptive power supply sense Control & Sense I/O Pins LASI Reset Transmitter ON/OFF Port address 4:0 MDIO Pins MOD DETECT Management data IO Management data clock High Speed I/O Pins Receiver lane 0:3 + Receiver lane 0:3 Transmitter lane 0:3 + Transmitter lane 0:3 Non connected pins Not connected Do not connect pins Do not connect 11, 15:16, 24 Avago Specific 13, 26, 38:39, 67:68 NC on module 41, 44, 47, 50 42, 45, 48, 51 55, 58, 61, 64 56, 59, 62, 65 O O I I XAUI per IEEE802.3ae clause 47 XAUI per IEEE802.3ae clause 47 XAUI per IEEE802.3ae clause 47 XAUI per IEEE802.3ae clause 47 14 17 18 O I/O I 1 kW pull down to ground on module 1.2 V per IEEE802.3ae clause 45.3 1.2 V per IEEE802.3ae clause 45.3 9 10 12 19:23 O I I I 1.2 V CMOS pull up on host 1.2 V CMOS pull up on module 1.2 V CMOS pull up on module 1.2 V CMOS pull up on module 1:3, 33:37, 40, 43, 46, 49 52:54, 57, 60, 63, 66, 69:70 5:6, 30:31 4, 32 7:8, 28:29 25 27 I I I I I Electrical ground 3.3 V power supply 5.0 V power supply Adaptive power supply (0.9 - 1.8 V) APS set connection APS sense connection
Pins
Direction
Function
11
Electrical Pin Out
Top of PCB
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 GND GND NOT CONNECTED NOT CONNECTED GND TX LANE3TX LANE3+ GND TX LANE2TX LANE2+ GND TX LANE1TX LANE1+ GND TX LANE0TX LANE0+ GND GND GND RX LANE3RX LANE3+ GND RX LANE2RX LANE2+ GND RX LANE1RX LANE1+ GND RX LANE0RX LANE0+ GND NOT CONNECTED NOT CONNECTED GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Bottom of PCB (as viewed from top of PCB)
GND GND GND 5.0V 3.3V 3.3V APS APS LASI RESET DO NOT CONNECT TX ON/OFF NOT CONNECTED MOD DETECT DO NOT CONNECT DO NOT CONNECT MDIO MDC PRTAD4 PRTAD3 PRTAD2 PRTAD1 PRTAD0 DO NOT CONNECT APS SET NOT CONNECTED APS SENSE APS APS 3.3V 3.3V 5.0V GND GND GND
Figure 6. Electrical Pin Out
12
Electrical Pin Out Definitions Table 9. Pin Function Definitions (Lower Row)
Pin No
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
Name
GND GND GND 5V 3.3 V 3.3 V APS APS LASI RESET DO NOT CONNECT TX ON/OFF NOT CONNECTED MOD DETECT DO NOT CONNECT DO NOT CONNECT MDIO MDC PRTAD4 PRTAD3 PRTAD2 PRTAD1 PRTAD0 DO NOT CONNECT APS SET NOT CONNECTED APS SENSE APS APS 3.3 V 3.3 V 5V GND GND GND
Direction
Function
Electrical ground Electrical ground Electrical ground
Note
I I I I I O I I
5.0 V power supply 3.3 V power supply 3.3 V power supply Adaptive power supply (0.9 - 1.8 V) Adaptive power supply (0.9 - 1.8 V) Logic high: normal operationLogic low: LASI asserted Logic high: normal operationLogic low: reset Avago specific; do not connect Pulled up inside module via 10 kW Logic high: transmitter onLogic low: transmitter off See Table 13
O
Pulled low inside module through 1 kW to GND Avago specific; do not connect Avago specific; do not connect
I/O I I I I I I I I I I I I I
Management data IO Management data clock Port address bit 4 Port address bit 3 Port address bit 2 Port address bit 1 Port address bit 0 Avago specific; do not connect APS set connection APS sense connection Adaptive Power Supply (0.9 - 1.8 V) Adaptive Power Supply (0.9 - 1.8 V) Power Power 5.0 V Power Supply Electrical Ground Electrical Ground Electrical Ground
13
Table 10. Pin Function Definitions (Upper Row)
Pin No
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Name
GND GND NOT CONNECTED NOT CONNECTED GND RX LANE 0+ RX LANE 0GND RX LANE 1+ RX LANE 1GND RX LANE 2+ RX LANE 2GND RX LANE 3+ RX LANE 3GND GND GND TX LANE 0+ TX LANE 0GND TX LANE 1+ TX LANE 1GND TX LANE 2+ TX LANE 2GND TX LANE3+ TX LANE3GND NOT CONNECTED NOT CONNECTED GND GND
Direction
Function
Electrical Ground Electrical Ground
Note
Electrical Ground O O O O O O O O Module XAUI Output Lane 0+ Module XAUI Output Lane 0Electrical Ground Module XAUI Output Lane 1+ Module XAUI Output Lane 1Electrical Ground Module XAUI Output Lane 2+ Module XAUI Output Lane 2Electrical Ground Module XAUI Output Lane 3+ Module XAUI Output Lane 3Electrical Ground Electrical Ground Electrical Ground I I I I I I I I Module XAUI Input Lane 0+ Module XAUI Input Lane 0Electrical Ground Module XAUI Input Lane 1+ Module XAUI Input Lane 1Electrical Ground Module XAUI Input Lane 2+ Module XAUI Input Lane 2Electrical Ground Module XAUI Input Lane 3+ Module XAUI Input Lane 3Electrical Ground
Electrical Ground Electrical Ground
14
Figure 7. Mechanical Dimensions Notes 1. All module and PCB pad dimensions are per X2 MSA Revision 2.0b unless otherwise noted in Figure 7.
15
Management Data Input/Output (MDIO) Interface
The MDIO interface provides a simple, two wire, serial interface to connect a station management entity (STA) and a managed PHY for the purpose of controlling the PHY and gathering status from the PHY. The management interface consists of the two wire physical interface, a frame format, a protocol specification for exchanging the frames and a register set that can be read and written using these frames. The two wires of the physical interface are the Management Data Clock (MDC) and the Management Data I/O (MDIO).
MDIO Timing relationship to MDC
MDIO is a bidirectional signal that can be sourced by the STA or the HFBR-707X2DEM. When the STA sources the MDIO signal, the STA shall provide a minimum of 10 ns of setup time and a minimum of 10 ns of hold time referenced to the rising edge of MDC (see Figure 8). When the MDIO signal is sourced by the HFBR-707X2DEM, it is sampled by the STA synchronously with respect to the rising edge of MDC. The clock output delay from the HFBR707X2DEM shall be a minimum of 0 ns and a maximum of 300 ns.
Management Data Clock (MDC)
The MDC is sourced by the Station Management entity (STA) to the PHY as the timing reference for transfer of information on the MDIO signal. MDC is an aperiodic signal that has no maximum high or low times.
Management Frame Format
The HFBR-707X2DEM has an internal address register which is used to store the address for MDIO reads and writes. This MDIO address register can be set by using an address frame that specifies the register address to be accessed within a particular port device. The following write, read or a post-read-increment-address frame to the same port device shall access the register whose address is stored in the HFBR-707X2DEM MDIO address register. An address frame should be followed immediately by its associated write, read or post-read-increment-address frame. Upon receiving a post-read-increment-address frame and having completed the read operation, the HFBR707X2DEM shall increment and store the address of the register accessed. If no address cycle is received before the next write, read or post-read-increment-address frame, then the HFBR-707X2DEM shall use the stored address for that register access. The Management Frame Format for Indirect Access is specified in Table 11.
Management Data I/O (MDIO)
MDIO is a bidirectional signal between the PHY (HFBR707X2DEM) and the STA. It is used to transfer control and status information. Data is always driven and sampled synchronously with respect to MDC. Figure 9 shows that MDIO open drain driver configuration.
MDC
tsu=10 ns min
MDIO (STA Sourced)
Data Valid
thd=10 ns min
MDC MDIO (HFBR-707X2DEM Sourced)
PRE - Preamble
Data Valid
tpd=0 ns min, 300 ns max
Figure 8. MDIO/MDC Timing
At the beginning of each transaction the STA shall send a preamble sequence of 32 contiguous logic one bits on MDIO with 32 corresponding cycles on MDC, to provide the HFBR-707X2DEM with a pattern that it can use to establish synchronization. The HFBR-707X2DEM must observe this preamble sequence before it responds to any transaction.
16
1.2 V pullup, R=10 k receive buffer MDIO pin Open drain driver COREGND Figure 9. MDIO open Drain Driver Configuration external capacitance loading C< 700 pF
Table 11. Frame Format
Management Frame Fields FRAME
ADDRESS WRITE READ READ INC
PRE
1...1 1...1 1...1 1...1
ST
00 00 00 00
OP
00 01 11 10
PRTAD
PRTAD[4:0] PRTAD[4:0] PRTAD[4:0] PRTAD[4:0]
DEVAD
DA[4:0] DA[4:0] DA[4:0] DA[4:0]
TA
10 10 Z0 Z0
ADDR/DATA
A[15:0] D[15:0] D[15:0] D[15:0]
IDLE
Z Z Z Z
ST - Start
The Start of Frame is indicated by a <00> pattern. This pattern ensures transitions from the default logic one line to zero and back to one.
PRTAD - Port Address
The Port Address is five bits, allowing 32 unique port addresses. HFBR-707X2DEM's port address is set through pins PRTAD<0:4>.
OP - Operation Code
The operation code field indicates the type of transaction being performed by the frame.
DEVAD - Device Address
The Device Address is five bits, allowing 32 unique devices per port. The HFBR-707X2DEM supports device addresses 1 (PMA/PMD), 3 (PCS) and 4 (PHY XS).
Table 12. OP Code Definitions
OP Code
00 01 11 10
TA - Turnaround
The Turnaround time is a two bit time spacing between the Register Address field and the Data field of a management frame to avoid contention during a read transaction (see IEEE 802.3ae).
Operation
Register Address Write Data Read Data Post Read Increment Address
ADDR/DATA
The Data/Address field is 16 bits. The first bit transmitted/ received is bit 15 and the last bit is bit 0.
IDLE
The idle condition is a high-impedance state. The MDIO line will be pulled to a one.
17
EEPROM Interface Volatile and Non-Volatile Registers
There are two main memory/register types in the HFBR707X2DEM which comply with the IEEE 802.3ae and XENPAK standard: volatile and nonvolatile. These areas can be further divided into user readable and writeable areas. At power up the module register space is initialized and, where appropriate, default values are loaded from the non user accessible nonvolatile memory. The user accessible nonvolatile memory is also uploaded entirely into the user accessible volatile memory. It is important to note that writes to the user accessible volatile memory are not stored to the corresponding user nonvolatile area and will therefore be lost upon a power down or reset. For such writes to be permanent the data
DEVICE MANAGEMENT INTERFACE - ADDRESS FRAME STRUCTURE MDC MDIO Write
32 "1"s 0 0 0 0 A4 A3 A0 R4 R3 R0 1 0 A15 A14 A1 A0
must be written first to the user accessible nonvolatile area and then a reload invoked via the NVR Control/Status register, see Register 1.32768.
Access
The XENPAK MSA related Nonvolatile Control/Status register is only needed for performing writes to the nonvolatile user accessible area within the HFBR-707X2DEM because nonvolatile memory cannot be written to by normal MDIO write cycles. Other writes to volatile memory and registers may be performed directly via normal MDIO write cycles. All volatile and nonvolatile locations may be read directly via MDIO read cycles, it is not necessary to use the NVR Control/Status register, other than for status.
Idle Preamble
ST
Op Code
PHY Address
Register Address Write
Turn Around
Address
Idle
DEVICE MANAGEMENT INTERFACE - WRITE FRAME STRUCTURE MDC MDIO Write
32 "1"s 0 0 0 1 A4 A3 A0 R4 R3 R0 1 0 D15 D14 D1 D0
Idle Preamble
ST
Op Code
PHY Address
Register Address Write
Turn Around
Data
Idle
DEVICE MANAGEMENT INTERFACE - READ INCREMENT FRAME STRUCTURE MDC MDIO READ INCREMENT
32 "1"s 0 0 1 0 A4 A3 A0 R4 R3 R0 Z 0 D15 D14 D1 D0
Idle Preamble
ST
Op Code
PHY Address Write
Register Address
Turn Around
Data Read
Idle
DEVICE MANAGEMENT INTERFACE - READ FRAME STRUCTURE MDC MDIO READ
32 "1"s 0 0 1 1 A4 A3 A0 R4 R3 R0 Z 0 D15 D14 D1 D0
Idle Preamble
ST
Op Code
PHY Address Write
Register Address
Turn Around
Data Read
Idle
Figure 10. MDIO Frame Formats
18
Read/Write Command (bit5)
The XENPAK MSA related 1.32768.5 register must be set to 1 to perform writes to the NVR and zero (read) otherwise a zero written to bit 5 initiates an NVR read. A 1 written to bit 5 initiates an NVR write. If the NVR register bit 5 is set to zero and the extended command bits set to 11 forces an upload of all values in the NVR to the volatile areas, including default register values. Such an upload is performed automatically after a hard or soft reset.
EEPROM Single Byte Read or Write Cycle
An EEPROM Single Byte Read/Write Cycle is initiated by setting MDIO EEPROM control register bits 1.32768.1:0 to 10. As for the 256 byte read/write commands, MDIO register 1.32768.5 determines if a read or a write cycle will be performed. The single byte EEPROM address is read from EEPROM control register 1.32768 bit15:8. The data is placed in/read from the associated MDIO register.
Monitors and Diagnostic Features
The LASI pin is used to indicate suboptimal performance in either the receive or transmit path. It can be used as an interrupt. It is the OR of the tx_alarm, rx_alarm and the ls_alarm signals each gated with their respective enables. The enables are read from MDIO register 1.36866, LASI control. LASI ={OR of (reg 1.36869.n `bit wise AND ` reg 1.36866.n) for n=0 to 15}.
EEPROM Checksum Checking
The HFBR-707X2DEM will perform a checksum calculation and compare after every successful 256 byte read. The checksum for comparison is in EEPROM register 118 =MDIO register 1.32893.7:0. The checksum is equal to the 8 LSB `s of the sum of bytes 0 to 117 of the EEPROM. The calculated checksum is stored in MDIO register 1.49156.15:8. The result of the calculated checksum compared with the one read from EEPROM is placed in MDIO register 1.49155.7.
ls_alarm
LS Alarm is latched high each time the link_status signal changes state. LS_ALARM is the output of this latch AND the LS_ALARM enable register. link_status is an indicator of the link health. link_status = {PMD signal detect (MDIO 1.10.0) AND PCS block_lock (MDIO 3.32.0) AND PHY_XS lane_alignment (MDIO 4.24.12)}
EEPROM 256 Byte Read Cycle
An EEPROM 256 Byte Read Cycle is initiated by setting MDIO bits 1.32768.0,1 to 0 and 1.32768.5 to 0. The information to be read from the EEPROM stored in the 256 MDIO registers. A 256 byte read is initiated on hot plug or reset.
Table 13. LASI Control Registers
Description
3.3V supply out of range APS supply out of range Reserved RX_ALARM TX_ALARM LS_ALARM
MDIO Status Registers (RO)
1.36869.5 1.36869.4 1.36869.3 1.36869.2 1.36869.1 1.36869.0
Type
RO RO RO RO RO/LH
MDIO Enable Registers (R/W)
1.36866.5 1.36866.4 1.36866.3 1.36866.2 1.36866.1 1.36866.0
Default
0 0 X 0 0 0
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Rx_alarm
rx_alarm is used to indicate a problem with the receive path. rx_alarm is the OR of several receive path status registers in MDIO registers 1.36867. The ORing of each term is enabled by a companion MDIO register in 1.36864 and the overall output is enabled by the RX_ALARM enable register (1.36866.2h). rx_alarm ={OR of (reg 1.36867 `bit wise AND ` reg 1.36864.. n) for n=0 to 15} AND {RX_ALARM enable (1.36866.2h})
tx_alarm
tx_alarm is used to indicate a problem with the transmit path. tx_alarm is the OR of several transmit path status registers in MDIO registers 1.36868 bit wise AND'd with the TX_ALARM enable register. The ORing of each term is enabled by a companion MDIO register in 1.36865. tx_alarm = {OR of (reg 1.36868 `bit wise AND' reg 1.36865) for n=0 to 15} AND {TX_ALARM enable (reg 1.36866.1)}
Table 14. Receive Alarm Registers
Description
WIS local fault Reserved Receive Optical Power fault PMA/PMD fault PCS fault Reserved RX_FLAG PHY XS fault
MDIO Status Registers (RO)
1.36867.9 1.36867.6-8 1.36867.5 1.36867.4 1.36867.3 1.36867.2 1.36867.1 1.36867.0
Mirrors
Type
RO RO/LH1
MDIO Enable Registers (R/W)
1.36864.9 1.36864.6-8 1.36864.5 1.36864.4 1.36864.3 1.36864.2 1.36864.1 1.36864.0
Default
0 X 1 1 1 X 0 1
1.8.10 3.8.10
RO/LH RO/LH RO
4.8.10
RO/LH
1. This bit will be read only if bit 9 of the Optional Settings Register at 1.49175 is set to 1, and RO/LH if it is set to 0.
Table 15. Transmit Alarm Registers
Description
Laser Bias Current fault Laser Temp fault Laser Output Power fault Transmit fault Reserved PMA/PMD fault PCS fault Reserved TX_FLAG PHY XS fault
MDIO Status Registers (RO)
1.36868.9 1.36868.8 1.36868.7 1.36868.6 1.36868.5 1.36868.4 1.36868.3 1.36868.2 1.36868.1 1.36868.0
Mirrors
Type
RO RO RO RO/LH -
MDIO Enable Registers (R/W)
1.36865.9 1.36865.8 1.36865.7 1.36865.6 1.36865.5 1.36865.4 1.36865.3 1.36865.2 1.36865.1 1.36865.0
Default
1 1 1 0 X 1 1 X 0 1
1.8.11 3.8.11
RO/LH RO/LH RO
4.8.11
RO/LH
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Loopbacks
When in any system (PMA, PCS or PHY XS system) loopback mode the HFBR-707X2DEM shall accept data from the transmit path and return it on the receive path. During PMA or PHY XS system loopback, a continuous stream of zeros is propagated through the remaining transmit data path. In PCS loopback mode, a continuous pattern of 0x00FF is propagated through the remaining transmit data path. Transmit data will be propagated through the remaining transmit data path instead if the associated `loopback data output enable bit' is set high for the enabled loopback mode. When in PMA network loopback mode, the recovered and retimed 10.3125 GBd signal is looped to the transmitter. The receive path XAUI output data will be received data. In PHY XS network loopback the recovered received data is looped back to the transmit path in the XAUI block. Enabling of more than one loopback path is invalid.
Reset Operation
Writing a `1' to any of MDIO registers 1.0.15, 3.0.15 or 4.0.15 causes all the HFBR-707X2DEM registers to be reset to their default values. These bits are all self-clearing after the reset function is complete. Pulling the RESET pin low causes a full chip reset. Writes to any bits of the Control register while the RESET is asserted are ignored. All status and control registers are reset to their default states. The NVR read sequence is started when RESET goes high. MDIO register bits 1.0.15, 3.0.15, and 4.0.15 will be held to 1 until the reset sequence is complete.
Table 16. Loopback Summary
loopback direction
Tx -> Rx Tx -> Rx
loopback name
PMA system loopback PCS loopback
loopback control register
1.0.0 3.0.14 4.49152.14 1.49153.4 4.0.14
bypassed path default output
stream of 0's 0x00FF stream of 0's received data received data
data output enable register
3.49152.5 3.49152.5 4.49152.15 NA NA
bypassed path output control' =1
transmit data transmit data transmit data NA NA
PHY XS system loopback Tx -> Rx PMA network loopback PHY XS network loopback Rx -> Tx Rx -> Tx
21
22
XAUI LANE 0 XAUI LANE 0 XTAL CDR PLL Driver PLL
PHY XS NETWORK LOOPBACK LANE 0
Figure 11. HFBR-707X2DEM Loopback Modes
XAUI LANE 3 XAUI LANE 2 XAUI LANE 1
Mux
PHY XS Network Loopback 4.0.14=1
SIPO and code word alignment, with |K| char
Lane Alignment, with |A| character. 8B/10B Encoder
8B/10B Decoder
PHY XS System Loopback 4.49152.14=1
Rate adjust
Rate adjust by add drop off |R| character
PHY XS System Loopback 4.49152.14
XAUI LANE 3
XAUI LANE 2
64B/66B Decoder
Descrambler 1+X
XAUI LANE 1
39
PHY XGXS SYSTEM LOOPBACK LANE 0
64B/66B Encoder
+X 58
Scrambler 1+X
39
+X 58
64B/66B 1:0 Block sync
PCS System Loopback 3.0.14=1
PCS SYSTEM LOOPBACK
Frame Recovery (block sync)
Rate Adjust & Frame
Tx XTAL PLL
De Mux
Mux
PMA Network Loopback
PMA Network Loopback 1.49153.4=1 System Loopback 1.0.0=1
CDR
PMA System Loopback
EDC Rx Opto
Tx Opto
XENPAK Digital Optical Monitoring (DOM) Overview
The XENPAK Digital Optical Monitoring (DOM) interface is a derivative of SFF-8472: Digital Diagnostic Monitoring Interface for Optical Transceivers appropriate to XENPAK transceivers. This specification defines a 256 byte block of register space that is accessible over the 2 wire serial MDIO/MDC interface. A memory map is used to access measurements of transceiver temperature, receive optical power, laser output power, and laser bias current through the 2 wire serial MDIO/MDC interface. Support for these measurements is indicated through the capability registers (1.32890 : DOM Capability and 1.41071: DOM Capability - Extended). The transceiver generates this monitoring data by digitization of internal analog signals, which are calibrated to absolute measurements. Measured parameters are reported in 16 bit data fields (two concatenated bytes). Alarm flags are required so DOM indicators can be made inputs to the Link Alarm Status Interrupt (LASI) function. Calibrated alarm and warning threshold data is written during device manufacture.
Table 17. XENPAK Digital Optical Monitoring MDIO Register Space
Device
1 1 1 1 1
From Decimal
32890 40960 41056 41070 41216
Hex
807A A000 A060 A06E A100
To Decimal
32890 40999 41065 41071 41216
Hex
807A A027 A069 A06F A100
Register Name
DOM Capability Alarm and Warning Thresholds Monitored A/D Values Optional Status and DOM Extended Capabilities Optional DOM Control/Status
Table 18. Register 1.32890 - DOM Capability
Bit(s)
1.32890.7
Name
DOM Register Implemented DOM Implemented WDM capability
Description
DOM Control/Status Register: 0 = not implemented 1 = implemented Set when DOM implemented WDM lane by lane DOM capability: setting this bit indicates that registers A0CO-A0FF are valid. Setting this bit will NOT override indications placed in register A06F (DOM capability) Laser bias scale factor: 0 = 2 A 1 = 10 A Reserved Address of external DOM device
R/W1
RO
Default Value
Specified by Customer
1.32890.6 1.32890.5
RO RO
mirrors 1.32890.7 0
1.32890.4
Laser bias scale
RO
1
1.32890.3 1.32890.2:0 External DOM
RO RO
X XXX
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Alarm and Warning Flags
MDIO registers 1.41072 to 1.41079 contain alarm and warning flags that monitor A/D values in registers 1.410561.41065. Two flag types are defined: * Alarm flags (registers 1.41072 - 1.41073) associated with transceiver temperature, receive optical power, laser output power, and laser bias current. Alarm flags indicate conditions likely to be associated with an inoperational link and cause for immediate action. * Warning flags (registers 1.41076 - 1.41077) associated with transceiver temperature, receive optical power, laser output power, and laser bias current. Warning flags indicate conditions outside the normally guaranteed bounds, but not necessarily causes of immediate link failures.
Table 19. Registers Alarm and Warning Flag Memory Map
Bit(s)
1.41072.7 1.41072.6 1.41072.4-5 1.41072.3 1.41072.2 1.41072.1 1.41072.0 1.41073.7 1.41073.6 1.41073.0-5 1.4107475.7:1 1.41076.7 1.41076.6 1.41076.4-5 1.41076.3 1.41076.2 1.41076.1 1.41076.0 1.41077.7 1.41077.6
Name
Transceiver Temp High Alarm Transceiver Temp Low Alarm Reserved Laser Bias Current High Alarm Laser Bias Current Low Alarm Laser Output Power High Alarm Laser Output Power Low Alarm Receive Optical Power High Alarm Receive Optical Power Low Warning Reserved Reserved Transceiver Temp High Warning Transceiver Temp Low Warning Reserved Laser Bias Current High Warning Laser Bias Current Low Warning Laser Output Power High Warning Laser Output Power Low Warning Receive Optical Power High Warning Receive Optical Power Low Warning
Description
Set when transceiver temp exceeds high alarm level Set when transceiver temp is below low alarm level Set when laser bias current exceeds high alarm level Set when laser bias current is below low alarm level Set when laser output power exceeds high alarm level Set when laser output power is below low alarm level Set when receive optical power exceeds high alarm level Set when receive optical power is below low warning level
Type
RO RO RO RO RO RO RO RO
Default Value (dec)
0 0 0 0 0 0 0 0
Set when transceiver temp exceeds high warning level Set when transceiver temp is below low warning level Set when laser bias current exceeds high warning level Set when laser bias current is below low warning level Set when laser output power exceeds high warning level Set when laser output power is below low warning level Set when receive optical power exceeds high warning level Set when receive optical power is below low warning level
RO RO RO RO RO RO RO RO
0 0 0 0 0 0 0 0
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Operation
A top-level block diagram of Digital Optical Monitoring (DOM) incorporated into the Link Alarm Status Interrupt (LASI) function is shown in Figure 12.
TX Alarm Flags 1.41072
TX_FLAG to bit 1 of TX_ALARM
TX Flag Control 1.36870
RX Alarm Flags 1.41073
RX_FLAG to bit 1 of RX_ALARM
TX Flag Control 1.36870
Figure 12. DOM/LASI Block Diagram
TX_FLAG Status
Assertion of TX_FLAG indicates that one or more of the transmitter operating parameters (transceiver temperature, laser bias current, or laser output power) exceeds the alarm levels. Tx alarm flags only monitor A/D values in registers 1.41056-1.41069. TX_FLAG shall be the logic OR of the bits in register 1.41072. The contents of the TX_FLAG status register are shown below. Bit 1 of TX_ALARM (TX_FLAG) will have the properties of latch high, clear on read (note that if the condition exists following register read, the bit will not be cleared).
TX_FLAG Control
TX_FLAG may be programmed to assert only when specific transmit operation parameters exceed their alarm levels. The programming is performed by writing the contents of a mask register located at offset 1.36870. The contents of register 1.41072 shall be AND'ed with the contents of register 1.36870 prior to application of the OR function that generates the TX_FLAG signal.
Table 20. Register 1.36870: TX_FLAG Control Bits
Bit(s)
1.36870.7 1.36870.6 1.36870.5:4 1.36870.3 1.36870.2 1.36870.1 1.36870.0 Current High enable Current low enable LoP high enable LoP low enable
Name
Temp high Enable Temp low enable
Description
Transceiver Temp High Alarm Enable Transceiver Temp Low Alarm Enable Reserved Laser Bias Current High Alarm Enable Laser Bias Current Low Alarm Enable Laser Output Power High Alarm Enable Laser Output Power Low Alarm Enable
Type
RW RW RW RW RW RW RW
Default Value (dec)
0 0 0 0 0 0 0
25
RX_FLAG Status
Assertion of RX_FLAG indicates that one or more of the receiver operating parameters (receive optical power) exceeds the alarm levels. Rx alarm flags only monitor A/D values in registers 1.41056-1.41070. RX_FLAG shall be the logic OR of the bits in register 1.41073. The contents of the RX_FLAG status register are shown below. Bit 1 of RX_ALARM (RX_FLAG) will have the properties of latch high, clear on read (note that if the condition exists following register read, the bit will not be cleared).
RX_FLAG Control
RX_FLAG may be programmed to assert only when specific receive operation parameters exceed their alarm levels. The programming is performed by writing the contents of a mask register located at offset 1.36871. The contents of register 1.41072 shall be AND'ed with the contents of register 1.36871 prior to application of the OR function that generates the RX_FLAG signal.
Table 21. Register 1.36871: RX_FLAG Control Bits
Bit(s)
1.36871.7 1.36871.6 1.36871.5:0
Name
Rx power High enable Rx power low enable
Description
Receive Optical Power High Alarm Enable Receive Optical Power Low Alarm Enable Reserved
Type
RW RW RW
Default Value (dec)
0 0 0
Regulatory Compliance
The HFBR-707X2DEM is intended to enable commercial system designers to develop equipment that complies with the various regulations governing Certification of Information Technology equipment (see Table 22).
Electromagnetic Interference (EMI)
Most equipment design utilizing these high speed transceivers from Avago Technologies will be required to meet the requirements of FCC in the United States, CENELEC EN55022 (CISPR 22) in Europe and VCCI in Japan. Performance of the HFBR-707X2DEM transceiver is dependent upon customer board and chassis design.
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD damage is important. The first case is during handling of the transceiver prior to plugging into the circuit board. It is important to use normal ESD handling precautions for ESD sensitive devices. These precautions include using grounded wrist straps, work benches and floor mats in ESD controlled areas. The second case to consider is static charges to the exterior of the equipment chassis containing the transceiver parts. To the extent that the SC duplex connector of the transceiver part is exposed outside of the equipment chassis, the HFBR-707X2DEM transceiver is designed to withstand types and levels of ESD indicated in Table 22 to enable equipment compliance to the system level criteria it is intended to meet.
Immunity
Equipment utilizing these transceivers will be subject to radio frequency electromagnetic fields in some environments. These transceivers have been characterized without the benefit of the normal equipment chassis enclosure and results are reported below. Performance of a system containing these transceivers within a well-designed chassis enclosure is expected to be better than the results of these tests without a chassis enclosure.
Laser Eye Safety
The HFBR-707X2DEM transceiver is a Class 1 laser product, compliant with IEC 60825-1:2001-8. The output radiation wavelength is in the 1260-1355 nm range. The maximum output power radiation of a module affected by a single fault is 5 mW. Also see table 22.
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Table 22. Regulatory Compliance
Feature General Electrostatic Discharge - Human Body Model Electrostatic Discharge - Charged Device Model Electrostatic Discharge - Contact Discharge Air Discharge Electromagnetic Interference Immunity Test Method Telcordia GR-468-CORE MIL STD 883 Method 3015 JEDEC JES D22-C101 IEC 61000-4-2 Performance Qualified in accordance with Remote terminal requirements 500 V 500 V 8000 V15000 V
FCC Class BCENELEC EN55022 Class B (CISPR 22B) VCCI Class 2 Variation of IEC 61000-4-3
Margins are dependant on customer board and chassis design Typically show no measurable effect from a 10 V/m field swept from 80 MHz to 10 GHz applied to the transceiver without a chassis enclosure. CDRH: in progress TUV: in progress
Laser Eye Safety
US FDA CDRH AEL Class 1 US 21 CFR, Subchapter J, 1040.10 and Laser Notice # 50 (IEC) EN60825-1:2001-8
Component Recognition
Underwriters Laboratories and Canadian Standards Association Joint Component Recognition for Information Technology Equipment Including Electrical Business Equipment
UL certificate number PENDING
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For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies , Limited, in the United States and other countries. Data subject to change. Copyright (c) 2006 Avago Technologies, Limited. All rights reserved. AV02-0197EN - May 22, 2007
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